sampling gate मीनिंग इन हिंदी

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3. The associated equipment would look for a rising amplitude that indicated the start of the signal pulse, and then use sampling gates to extract the carrier phase.
4. The result of this final operation would become negative during a very specific and stable part of the rising edge of the pulse, and this zero-crossing was used to trigger a very short-time sampling gate.
5. However, during the active falling of the control signal, when the control signal is between V2 and V3, transistors Q5, Q6, Q7, and Q8 are all " on " ( and Q9, Q10, Q11, and Q12 all " off " ) resulting in the sampling gate being turned on.
6. Similarly, if the level of the control signal at the end of its falling transition is less than V2 by a few tenths of a volt, transistors Q11 and Q12 are " on " and transistors Q5 and Q6 are " off ", resulting in the output nodes being pulled up to Vdd, and the sampling gate again being turned off.
7. If the control signal is initially greater than V3 by more than a few tenths of a volt, transistor Q9 and Q10 are " on " ( biased into the forward conduction region ) and transistors Q7 and Q8 are " off " ( biased so that essentially no current flows ), resulting in the output nodes being pulled up to Vdd, causing the sampling gate to be turned " off " ( the output nodes contain no signal ).